I think given enough thought put into naming of signals and ports, many of such lines can be replaced with .* syntax in verilog (which basically connects all ports to signals that have the same name, but for that they have to have identical names of course). In case .* feels too obscure, still it is possible to omit signal names, like: (.reset, .clk, …) (if I'm not mistaken…).
From the design perspective, having names that are identical on both sides will add more clarity and prevent possible errors (to illustrate, you can think about MISO↔MISO and MOSI↔MOSI in SPI vs TX↔RX RX↔TX in UART).
Currently in many places there are lines like this (whether it's in Verilog or in VHDL does not really matter):
I think given enough thought put into naming of signals and ports, many of such lines can be replaced with
.*
syntax in verilog (which basically connects all ports to signals that have the same name, but for that they have to have identical names of course). In case.*
feels too obscure, still it is possible to omit signal names, like:(.reset, .clk, …)
(if I'm not mistaken…).From the design perspective, having names that are identical on both sides will add more clarity and prevent possible errors (to illustrate, you can think about MISO↔MISO and MOSI↔MOSI in SPI vs TX↔RX RX↔TX in UART).