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Proxmark / proxmark3

Proxmark 3
http://www.proxmark.org/
GNU General Public License v2.0
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LF Sim Timing issues #72

Closed marshmellow42 closed 9 years ago

marshmellow42 commented 9 years ago

I've been testing the LF sim functions to see why they are so erratic as to their functionality. I believe it comes down to the use of the clock in SimulateTagLowFrequency. could someone explain what GPIO_SSC_CLK measures?

let me illustrate the issue: a standard HID FSK2a tag should have waves 10 samples and 8 samples long depending on whether it is bit 1 or bit 0. so digitally it should be 1111100000 and 11110000.

if this is sent through the SimulateTagLowFrequncy the output has 2 errors.

  1. the number of samples have lengthened to 11111110000000 and 11111000000 so our clock is too slow
  2. if you compensate for by reducing the bits sent to the function then the second issue becomes obvious: the transition between bit 1s and bit 0s creates extra 0 waves. So going from 1111000011110000 to 1111100000 translates 11110000001111100000 (added 2 extra 0 bits)

img1: bad timing: fsk-sim-bad timing

img2: bad transition: fsk-sim-bad bit transition

any thoughts?

I can get ASK clocks of 32 or greater to work fine but the lower the clock the worse this affects things.

pwpiwi commented 9 years ago

Anything else we want included in 2.0.0-final?

I have another FPGA bugfix in hi_iso14443.v in testing and will commit on Monday morning. Together with @marshmellow42's last fixes this should go into 2.0.0-final. And I might commit the fix for issue #73 on Monday evening...

pwpiwi commented 9 years ago

Couldn't continue with testing yesterday. @holiman: up to you to decide when you want to do the "final" tagging. I personally don't care if these fixes go to 2.0.0.-final or the next release. I am quite sure that these won't be the last fixes anyway...

pwpiwi commented 9 years ago

Pushed two commits.