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Purdue-SoCET / vito-uart

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Vendoring bugged version of `BaudRateGen` #1

Open nickelpro opened 2 weeks ago

nickelpro commented 2 weeks ago

Hiya @yashsng44 @limichael246, I'm the "vito" in vito-uart

You've got a version of BaudRateGen vendored (meaning, "copied entirely") in your branch, Michael-Yash-Edits, under AHBUart_dependencies.sv

The problem is the totalWait calculation. This number is supposed to be the remainder of the rate ticks after division by the Oversample. But if we take a look at the code:

totalWait = rate - {rxRate, 4'b0};

Well, clearly I didn't do that, and neither Oversample or rxShift (which is $clog2(Oversample)) appear here at all. This represents a hardcoded assumption that Oversample == 16.

The fix is pretty simple, what this really wants to do is grab the lower rxShift bits of the rate, so something like this:

totalWait = txWidth'(rate[rxShift-1:0]);

This fix is implemented upstream, which I also did a new FuseSoC release for.

This is not a problem for already taped out code, this is only a problem if anyone changed the Oversample parameter to something other than 16, which I'm pretty sure never happened at Purdue. Pinging @cole-nelson just to say hi and to say maybe bump PurdNyUart to 2.0.3 in any code its floating around in.

cole-nelson commented 2 weeks ago

Vito,

Glad to hear from you, and thanks for pointing this out. I'll make sure this is picked up for the next tapeout.

What @yashsng44 and @limichael246 were working on with this was a standalone tapeout of this UART module for TinyTapeout, which was just submitted in the last few days. We're supposed to get silicon back sometime next semester I believe; I'll try to keep you in the loop on that once we're able to test it.

We're also working on adding support for hardware flow control (RTS/CTS) in the near future, though this tapeout side-quest ended up taking priority.