Rewrite - Project

[rodrigomelo9]

• [x] New __init__:

  tool = TOOLNAME
  project = PROJNAME
  outdir = DIRPATH
  meta = {
  part: PARTNAME,
  files: [
  {path: FILEPATH, type: FILETYPE, library: LIBNAME, options: OPTIONS},
  {path: FILEPATH, type: FILETYPE, library: LIBNAME, options: OPTIONS},
  {path: FILEPATH, type: FILETYPE, library: LIBNAME, options: OPTIONS}
  ],
  top: TOPNAME,
  params: [
  {name: PARAMNAME, value: PARAMVALUE},
  {name: PARAMNAME, value: PARAMVALUE}
  ],
  vlog_includes: [PATH1, PATH2, PATH3],
  vlog_defines: [
  {name: DEFINENAME, value: DEFINEVALUE},
  {name: DEFINENAME, value: DEFINEVALUE}
  ],
  vhdl_arch: ARCHNAME,
  hooks: {
  prefile: [CMMD1, CMMD2],
  project: [CMMD1, CMMD2],
  preflow: [CMMD1, CMMD2],
  postsyn: [CMMD1, CMMD2],
  postpar: [CMMD1, CMMD2],
  postbit: [CMMD1, CMMD2]
  }
  options: OPTIONS
  }

• Change openflow to yosys-nextpnr
• [x] Remove set_outdir
• [x] Move set_param to add_param
• [x] Move add_path to add_vlog_include
• [x] Add add_vlog_define
• [x] Add set_vhdl_arch
• [x] Change imp to par
• [x] Change generate to make
• [x] Change transfer to prog, which only will support fpga (bitstream and position are the only options)
• [x] Remove set_bitstream (absorbed by prog)

[rodrigomelo9]

Already done on rewrite branch