Functions with port lists can't be parsed

[noloerino]

The most recent version of pyverilog (commit 2a42539) does not support parsing function definitions where a port list is provided, like the following example:

module TOP(CLK, RST_X);
  input CLK;
  input RST_X;
  reg [3:0] cnt;

  function [3:0] inc(input [3:0] in); // <-- The input port is declared here, instead of on a separate line.
    if(&inc) begin
      inc = 0;
    end else begin
      inc = in + 1;
    end
  endfunction

  always @(posedge CLK or negedge RST_X) begin
    if(!RST_X) begin
      cnt <= 0;
    end else begin
      cnt <= inc(cnt);
    end
  end
endmodule

Running the dataflow analyzer raises this error message: pyverilog.vparser.parser.ParseError: line:3: before: "("

I have a PR ready that adds support for this (will link here after I make it), as well as a minimal test case.