search

PyHDI / Pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL
Apache License 2.0
619 stars 173 forks source link

[wip] Add support for functions declarations with port list #101

Open noloerino opened 2 years ago

noloerino commented 2 years ago

Addresses #100.

This code may allow illegal output definitions as well (such as function [3:0] f(output a); endfunction), though this case seems somewhat pathological. Fixing it would require adding a few more parser rules, which I can do if requested.

Please let me know if any other changes should be made.

noloerino commented 2 years ago

I did some more testing, and it seems like there's still some edge cases to fix. I'll let you know when this is ready for review.