PyHDI / Pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL
Apache License 2.0
640 stars 180 forks source link

Support SVA assert/assume #103

Open zhanghongce opened 2 years ago

zhanghongce commented 2 years ago

This pull request partially address the issue (https://github.com/PyHDI/Pyverilog/issues/87) as it adds support for assert property (...), always @(...) begin assert (...); end, assume property (...), always @(...) begin assume (...); end

Of course, some more work is needed in order to support @(posedge clk) inside the property.