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PyHDI / Pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL
Apache License 2.0
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Extracting design information via API #108

Open svenka3 opened 2 years ago

svenka3 commented 2 years ago

I like the examples provided such as parser, dataflow etc. Thanks a lot for doing this great work!

Say I want to use PyVerilog to query design information such as:

  1. ports
  2. All net names
  3. All escaped identifiers etc.

How do I approach? I looked at SignalAnalyze, visit_ports etc. but not clear on what the node argument and how to pass it. Any inputs please