PyHDI / Pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL
Apache License 2.0
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Unsized numbers without base not supported #116

Open Louis-DR opened 1 year ago

Louis-DR commented 1 year ago

Hello,

I noticed that unsized literal number constants with the base specified ('d0) are supported but if the base is not specified ('d) it raises a ParseError exception :

module top (
  output [7:0] q
);

assign q = '0;

endmodule
>>> python3 examples/example_parser.py top.v
Generating LALR tables
WARNING: 183 shift/reduce conflicts
Traceback (most recent call last):
  File "/Users/louis/Workspace/Pyverilog/examples/example_parser.py", line 55, in <module>
    main()
  File "/Users/louis/Workspace/Pyverilog/examples/example_parser.py", line 45, in main
    ast, directives = parse(filelist,
                      ^^^^^^^^^^^^^^^
  File "/Users/louis/Workspace/Pyverilog/pyverilog/vparser/parser.py", line 2371, in parse
    ast = codeparser.parse()
          ^^^^^^^^^^^^^^^^^^
  File "/Users/louis/Workspace/Pyverilog/pyverilog/vparser/parser.py", line 2349, in parse
    ast = self.parser.parse(text, debug=debug)
          ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/Users/louis/Workspace/Pyverilog/pyverilog/vparser/parser.py", line 77, in parse
    return self.parser.parse(text, lexer=self.lexer, debug=debug)
           ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/Library/Frameworks/Python.framework/Versions/3.11/lib/python3.11/site-packages/ply/yacc.py", line 333, in parse
    return self.parseopt_notrack(input, lexer, debug, tracking, tokenfunc)
           ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/Library/Frameworks/Python.framework/Versions/3.11/lib/python3.11/site-packages/ply/yacc.py", line 1063, in parseopt_notrack
    lookahead = get_token()     # Get the next token
                ^^^^^^^^^^^
  File "/Users/louis/Workspace/Pyverilog/pyverilog/vparser/lexer.py", line 51, in token
    return self.lexer.token()
           ^^^^^^^^^^^^^^^^^^
  File "/Library/Frameworks/Python.framework/Versions/3.11/lib/python3.11/site-packages/ply/lex.py", line 386, in token
    newtok = self.lexerrorf(tok)
             ^^^^^^^^^^^^^^^^^^^
  File "/Users/louis/Workspace/Pyverilog/pyverilog/vparser/lexer.py", line 259, in t_error
    self._error(msg, t)
  File "/Users/louis/Workspace/Pyverilog/pyverilog/vparser/lexer.py", line 263, in _error
    self.error_func(msg, location[0], location[1])
  File "/Users/louis/Workspace/Pyverilog/pyverilog/vparser/parser.py", line 67, in _lexer_error_func
    raise ParseError('%s: %s' % (coord, msg))
pyverilog.vparser.parser.ParseError:  line:5 column:13: Illegal character "'"

Note that some tools appear to treat '0 and 'd0 differently : ModelSim

I have never worked with lex or yacc but I might dig into it to try implementing this.

YSJL commented 11 months ago

Hey Louis were you able to fix this implementation?

YSJL commented 11 months ago

For whoever is going through this issue, you can edit lexer.py, parser.py, ast.py using already existing structures.

For lexer,py:

For parser.py:

For ast.py: