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PyHDI / Pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL
Apache License 2.0
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unsufficient parse for large scale verilog design #118

Open ZhaoYunfei123 opened 1 year ago

ZhaoYunfei123 commented 1 year ago

I'm tring to use pyverilog to parse one large scale design, but the ast.show() can't display all module's AST. How can I get all module's AST ?