search

PyHDI / Pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL
Apache License 2.0
619 stars 173 forks source link

Preprocessing Issue when included file is in different directory #123

Closed YSJL closed 12 months ago

YSJL commented 12 months ago

Hi I am using PyVerilog version 1.3.0 It looks like the preprocesser is unable to get the file for the included option when it is located other than the directory where the script is executed. define.vh & pipeline.v in Same Folder image

Same Folder Test Works image github_samefolder_preproc_test.txt

But when it is copied into the parent folder and erased from the original directory image

The preprocess script does not work image

The symptom also occurs when I directly use paths which the files are located image

These are the verilog files used for testing verilog_files.zip

YSJL commented 12 months ago

It works when I use the -I option with the path of the directory the included file is located rather than the path to the file itself!