PyHDI / Pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL
Apache License 2.0
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parser error #126

Open 1353369570 opened 1 year ago

1353369570 commented 1 year ago

when exculd: ast, directives = parse(file, preprocess_include="", preprocess_define="") Got the following error:

File "C:\Users\Administrator\AppData\Roaming\Python\Python37\site-packages\pyverilog\vparser\parser.py", line 2338, in parse ast = codeparser.parse() File "C:\Users\Administrator\AppData\Roaming\Python\Python37\site-packages\pyverilog\vparser\parser.py", line 2315, in parse text = self.preprocess() File "C:\Users\Administrator\AppData\Roaming\Python\Python37\site-packages\pyverilog\vparser\parser.py", line 2309, in preprocess self.preprocessor.preprocess() File "C:\Users\Administrator\AppData\Roaming\Python\Python37\site-packages\pyverilog\vparser\preprocessor.py", line 86, in preprocess subprocess.call(cmd) File "C:\Users\Administrator\AppData\Local\Programs\Python\Python37\lib\subprocess.py", line 323, in call with Popen(*popenargs, **kwargs) as p: File "C:\Users\Administrator\AppData\Local\Programs\Python\Python37\lib\subprocess.py", line 775, in init restore_signals, start_new_session) File "C:\Users\Administrator\AppData\Local\Programs\Python\Python37\lib\subprocess.py", line 1178, in _execute_child startupinfo)