PyHDI / Pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL
Apache License 2.0
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Unsized numbers without base solution #127

Open YSJL opened 1 year ago

YSJL commented 1 year ago

I had the same problem as issue #116 However, I was able to fix the problem by adding a new type of number with the provided structure. Already made a comment on said issue, but making a new one for visibility.

You can edit lexer.py, parser.py, ast.py using already existing structures. For lexer,py:

For parser.py:

For ast.py: