PyHDI / Pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL
Apache License 2.0
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TypeError: generate() got an unexpected keyword argument 'reorder' line 100 in Pyverilog/examples/example_graphgen.py #131

Open zhangshuaiAA9 opened 4 months ago

zhangshuaiAA9 commented 4 months ago

python3 Pyverilog/examples/example_graphgen.py -t top -s top.led test.v Generating LALR tables WARNING: 183 shift/reduce conflicts Traceback (most recent call last): File "./examples/example_graphgen.py", line 107, in main() File "./examples/example_graphgen.py", line 100, in main graphgen.generate(target, walk=options.walk, identical=options.identical, TypeError: generate() got an unexpected keyword argument 'reorder'

in example_graphgen.py", line 100,

96    graphgen = VerilogGraphGenerator(options.topmodule, terms, binddict,
97                                     resolved_terms, resolved_binddict, constlist, options.outputfile)
98
99   for target in options.searchtarget:
100       graphgen.generate(target, walk=options.walk, identical=options.identical,
101                            step=options.step, reorder=options.reorder, delay=options.delay)

There is a parameter called rerorder,The problem is that the VerilogGraphGenerator class doesn't have the reorder parameter in the generate() method definition, but it is provided when called.

The following is part of the definition of VerilogGraphGenerator class in the /Pyverilog/pyverilog/dataflow/graphgen.py

26 class VerilogGraphGenerator(object):
    ..........
    ..........
57    def generate(self, signalname, identical=False, walk=True, step=1, do_reorder=False, delay=False):
        termname = util.toTermname(signalname)
        tree = self.treewalker.getTree(termname)

One of the parameters is called do_reorder

barnard33-233 commented 2 months ago

120 fixed this issue. But it looks like no one is maintaining this repo

shtaxxx commented 2 months ago

I'm sorry. These days I could not take a time for manage my software, but I still have a will to continue the update of Pyverilog and related ones.