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PyHDI / Pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL
Apache License 2.0
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sorting names option (by Alphabetical order) in the parser output #25

Open babainc opened 9 years ago

babainc commented 9 years ago

It should be great to have an option to sort the parameter/port/signals/portmap signals in their respective section (module/instance/etc). I'm trying to compare two differents version of a RTL code (IPs). Between two RTL versions, some signals/ports/parameter name can be not at the same location in the RTL code, or can be remamed. The goal will be to be a visual diff on the parser result of each RTL code to see exactly the modification and find easily the diff. Without any sorting, it is quite hard to see what is new or different between two RTL code.

lgomezr2116 commented 4 months ago

It should be great to have an option to sort the parameter/port/signals/portmap signals in their respective section (module/instance/etc). I'm trying to compare two differents version of a RTL code (IPs). Between two RTL versions, some signals/ports/parameter name can be not at the same location in the RTL code, or can be remamed. The goal will be to be a visual diff on the parser result of each RTL code to see exactly the modification and find easily the diff. Without any sorting, it is quite hard to see what is new or different between two RTL code.

Mmg