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PyHDI / Pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL
Apache License 2.0
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Added end_lineno to indicate the last line number in always, module, … #88

Closed dyadav7 closed 1 year ago

dyadav7 commented 3 years ago

This will help in knowing the end line number for always block, modules, statements, case statement.
User can than use this information for different usage:

  1. Find the smallest / biggest module
  2. Find smallest/biggest always blocks , case statements
  3. Use this information to create a new file that has these parts (blocks / modules / ..) commented out.
  4. ....
shtaxxx commented 3 years ago

Thanks! Let me review the code.