Open faruqui13 opened 3 years ago
Hi I was trying same test.v file provided in the example and I am getting following error:
python .\pyverilog-1.3.0\examples\example_controlflow_analyzer.py -t top .\Test.v Generating LALR tables WARNING: 183 shift/reduce conflicts FSM signal: top.count, Condition list length: 4 FSM signal: top.state, Condition list length: 5 Condition: (Eq, top.enable), Inferring transition condition Condition: (Ulnot, Eq), Inferring transition condition Condition: (Ulnot, Ulnot, Eq), Inferring transition condition SIGNAL NAME: top.state DELAY CNT: 0 0 --(top_enable>'d0)--> 1 1 --None--> 2 2 --None--> 0 Traceback (most recent call last): File ".\pyverilog-1.3.0\examples\example_controlflow_analyzer.py", line 93, in main() File ".\pyverilog-1.3.0\examples\example_controlflow_analyzer.py", line 84, in main fsm.tograph(filename=util.toFlatname(signame) + '.' + File "C:\Users\nidfaruq\Documents\Python\Verilog\pyverilog-1.3.0\pyverilog\controlflow\controlflow_analyzer.py", line 249, in tograph graph.layout(prog='dot') File "C:\Users\nidfaruq\Anaconda3\lib\site-packages\pygraphviz\agraph.py", line 1399, in layout data = self._run_prog(prog, ' '.join([args, "-T", fmt])) File "C:\Users\nidfaruq\Anaconda3\lib\site-packages\pygraphviz\agraph.py", line 1364, in _run_prog raise IOError(b"".join(errors).decode(self.encoding))
Hi I was trying same test.v file provided in the example and I am getting following error:
python .\pyverilog-1.3.0\examples\example_controlflow_analyzer.py -t top .\Test.v Generating LALR tables WARNING: 183 shift/reduce conflicts FSM signal: top.count, Condition list length: 4 FSM signal: top.state, Condition list length: 5 Condition: (Eq, top.enable), Inferring transition condition Condition: (Ulnot, Eq), Inferring transition condition Condition: (Ulnot, Ulnot, Eq), Inferring transition condition SIGNAL NAME: top.state DELAY CNT: 0 0 --(top_enable>'d0)--> 1 1 --None--> 2 2 --None--> 0 Traceback (most recent call last): File ".\pyverilog-1.3.0\examples\example_controlflow_analyzer.py", line 93, in
main()
File ".\pyverilog-1.3.0\examples\example_controlflow_analyzer.py", line 84, in main
fsm.tograph(filename=util.toFlatname(signame) + '.' +
File "C:\Users\nidfaruq\Documents\Python\Verilog\pyverilog-1.3.0\pyverilog\controlflow\controlflow_analyzer.py", line 249, in tograph
graph.layout(prog='dot')
File "C:\Users\nidfaruq\Anaconda3\lib\site-packages\pygraphviz\agraph.py", line 1399, in layout
data = self._run_prog(prog, ' '.join([args, "-T", fmt]))
File "C:\Users\nidfaruq\Anaconda3\lib\site-packages\pygraphviz\agraph.py", line 1364, in _run_prog
raise IOError(b"".join(errors).decode(self.encoding))
OSError: Format: "dot" not recognized. Use one of: