PyHDI / Pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL
Apache License 2.0
619 stars 173 forks source link

gate level netlist to rtl #91

Open very3b opened 3 years ago

very3b commented 3 years ago

Hi, i am tring to run gate level netlist and analyze its datapath, seems got lots error, is that possible to so? File "examples/example_parser.py", line 55, in main() File "examples/example_parser.py", line 47, in main preprocess_define=options.define) File "/app/proj/socv/Pyverilog/pyverilog/vparser/parser.py", line 2338, in parse ast = codeparser.parse() File "/app/proj/socv/Pyverilog/pyverilog/vparser/parser.py", line 2316, in parse ast = self.parser.parse(text, debug=debug) File "/app/proj/socv/Pyverilog/pyverilog/vparser/parser.py", line 77, in parse return self.parser.parse(text, lexer=self.lexer, debug=debug) File "/home/itmgr/anaconda3/lib/python3.7/site-packages/ply/yacc.py", line 333, in parse return self.parseopt_notrack(input, lexer, debug, tracking, tokenfunc) File "/home/itmgr/anaconda3/lib/python3.7/site-packages/ply/yacc.py", line 1201, in parseopt_notrack tok = call_errorfunc(self.errorfunc, errtoken, self) File "/home/itmgr/anaconda3/lib/python3.7/site-packages/ply/yacc.py", line 192, in call_errorfunc r = errorfunc(token) File "/app/proj/socv/Pyverilog/pyverilog/vparser/parser.py", line 2268, in p_error self._raise_error(p) File "/app/proj/socv/Pyverilog/pyverilog/vparser/parser.py", line 2279, in _raise_error raise ParseError("%s: %s" % (coord, msg)) pyverilog.vparser.parser.ParseError: line:34: before: "if