How to append new assign to a module from verilog code?

[zilongwang123]

I have a test.v as: ''' module top ( input CLK, input RST, input add, output [7:0] led );

assign led = 8;

endmodule '''

I want to add a 'assign led = add + RST;' before endmodule, What's the easiest way to do this?