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PyHDI / veriloggen

Veriloggen: A Mixed-Paradigm Hardware Construction Framework
Apache License 2.0
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Indirect access RAM in Veriloggen.Thread.Stream #17

Closed shtaxxx closed 3 years ago

shtaxxx commented 6 years ago

I think Indirect access RAM can be realized based on stream.LUT.

shtaxxx commented 3 years ago

Similar features, such as strm.read_RAM, strm.write_RAM, strm.Scratchpad are already supported.