Supporting AXI Stream interface

[iitaku]

I'm requesting to support AXI Stream interface in veriloggen. It might be useful to design stream architecture.

[Nic30]

AXI stream is just handshaked interface and the implementation potentially exists.

However there are many features of the streaming interfaces which can make development of the hardware much easier.

• Do you require also proper support for the strb/keep signal ?
• Do you want raw access or more like memcpy access?
• Do you need control of endianity/ data alignment control?
• Do you need control of the frame merging/splitting?
• Do you need any specific settings to pipeline generatos which are using this interfaces? I mean like the output can be performed only this two interfaces are ready etc.

[iitaku]

@Nic30 Thanks for your comment.

In my understanding, ATM veriloggen can only generate module which has AXI Memory Mapped interface as their external interface. My proposal is make it possible to generate module with AXI Stream as external interface in the same way as AXI Memory Mapped.

IMHO, side channel signal might be mandatory in some cases. (e.g. Integrating Xilinx video IP core)

[shtaxxx]

AXI-Stream is support now!