PyHDI / veriloggen

Veriloggen: A Mixed-Paradigm Hardware Construction Framework
Apache License 2.0
306 stars 58 forks source link

Issues/54 add interval option to stypes.Counter #30

Closed lp6m closed 4 years ago

lp6m commented 4 years ago

Step: 0 1 2 3 4 5 6 7 x : x x 0 1 2 3 4 5 y : x x x x 0 0 0 1 #we want four zero!

The processing of `xcounter==3` takes 2 clock cycles, so counter _y_ is reset at _3rd clock cycle_, 2 cycles after the xcounter reset. And at _4th clock cycle_, `xcounter==3` holds, after two cycle, the value of _y_ counter is updated to 1.

This update can define counter with `interval` as following.
```python
cnt1 = strm.Counter()
cnt2 = strm.Counter(initval=1)
cnt3 = strm.Counter(initval=2, size=3)
cnt4 = strm.Counter(initval=3, interval=3)
cnt5 = strm.Counter(initval=4, interval=3, size=4)
cnt6 = strm.Counter(initval=4, step=2, interval=2)
step,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33
cnt1,x,x,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
cnt2,x,x,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32
cnt3,x,x,2,3,4,2,3,4,2,3,4,2,3,4,2,3,4,2,3,4,2,3,4,2,3,4,2,3,4,2,3,4,2,3
cnt4,x,x,3,3,3,4,4,4,5,5,5,6,6,6,7,7,7,8,8,8,9,9,9,10,10,10,11,11,11,12,12,12,13,13
cnt5,x,x,4,4,4,5,5,5,6,6,6,7,7,7,4,4,4,5,5,5,6,6,6,7,7,7,4,4,4,5,5,5,6,6
cnt6,x,x,4,4,6,6,8,8,10,10,12,12,14,14,16,16,18,18,20,20,22,22,24,24,26,26,28,28,30,30,32,32,34,34
shtaxxx commented 4 years ago

Thank you very much for very nice suggestion and implementation!