modify bug in readRAM when latency = 2

PyHDI / veriloggen

Veriloggen: A Mixed-Paradigm Hardware Construction Framework

Apache License 2.0

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Closed lp6m closed 4 years ago

lp6m commented 4 years ago

Fixed a bug that data port is not connected to wire when latency = 2 in read_RAM.

shtaxxx commented 4 years ago

Thanks!