search

PyHDI / veriloggen

Veriloggen: A Mixed-Paradigm Hardware Construction Framework
Apache License 2.0
306 stars 58 forks source link

Support for SystemVerilog Interfaces #42

Closed kiteloopdesign closed 3 years ago

kiteloopdesign commented 3 years ago

I think veriloggen does not support SV interfaces at the moment?

Are these on the pipeline? It should not be too much of an update to add suport for them given the syntax and structure is pretty similar to an usual verilog module

Thanks

shtaxxx commented 3 years ago

SystemVerilog support by Pyverilog is in-progress. After that, Veriloggen also supports SystemVerilog.

kiteloopdesign commented 3 years ago

Awesome, looking forward to it Thanks Shinya-San