PyHDI / veriloggen

Veriloggen: A Mixed-Paradigm Hardware Construction Framework
Apache License 2.0
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Case statement within combinational block #45

Closed kiteloopdesign closed 3 years ago

kiteloopdesign commented 3 years ago

I am trying to create a case statement within a combinational block, but I am not getting the blocking assignment it should be inferred. I am getting instead a non-blocking ("<=") assignment instead.

  always @(*) begin
    case(myvar)
      0: begin
        logic_wire <= 1;
      end
      default: begin
        logic_wire <= 5;
      end
    endcase
  end

Any idea on how to get this done? This is what my code looks like

myvar= m.Reg ('myvar', width = 4 , initval = 0 )
logic_wire= m.Reg ('logic_wire', width = 1 , initval = 0 )

decCond = []
decCond.append (vg.When ( 0 ) (logic_wire ( 1 )))
# ... more conditions ...
decCond.append (vg.When () (logic_wire ( 5 )))
m.Always( ) ( vg.Case (myvar) (* decCond ) )

Thanks!

LucasBraganca commented 3 years ago

Hi,

You need to pass the parameter True on the assignment to get the blocking assignment.

myvar= m.Reg ('myvar', width = 4 , initval = 0 )
logic_wire= m.Reg ('logic_wire', width = 1 , initval = 0 )

decCond = []
decCond.append (vg.When ( 0 ) (logic_wire ( 1 ,True)))
# ... more conditions ...
decCond.append (vg.When () (logic_wire ( 5 ,True)))
m.Always( ) ( vg.Case (myvar) (* decCond ) )
kiteloopdesign commented 3 years ago

Cool, obrigado Lucas, it does work indeed It would be awesome to throw all these examples into the wiki, it should not take long and save you guys a bunch of qeustions!