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PyHDI / veriloggen

Veriloggen: A Mixed-Paradigm Hardware Construction Framework
Apache License 2.0
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Slice in Wire with two dimension #47

Open LucasBraganca opened 2 years ago

LucasBraganca commented 2 years ago

Hi, I'm trying to do the following structure in Veriloggen:

m  = Module('test')
my_wire0 = m.Wire('my_wire0',8,2)
my_wire1 = m.Output('my_wire1',2)
my_wire1.assign(my_wire0[0][0:2])
print(m.to_verilog())

But an exception is raised!

shtaxxx commented 2 years ago

I test this code, and found that the current Slice operator supports only raw variables (such as Input, Output, Reg, and Wire) as the first argument. I will fixed in the next version.

Please use this workaround:

m  = Module('test')
my_wire0 = m.Wire('my_wire0', 8, 2)
my_wire1 = m.Output('my_wire1', 2)
tmp = m.TmpWireLike(my_wire0[0])
my_wire1.assign(tmp[0:2])