PyHDI / veriloggen

Veriloggen: A Mixed-Paradigm Hardware Construction Framework
Apache License 2.0
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Imcompatibility of `Module.Wire` and `Module.TmpWire` regarding the keyword arguments. #49

Closed estodi closed 1 year ago

estodi commented 1 year ago

When I try to switch automatically between TmpWire and Wire instead of using only Wire in codes like below (example from thread/ram.py), I thought it just works by replacing 'Wire' with 'TmpWire'.

interface = RAMInterface(m, name + '_%d' % i, datawidth, addrwidth,
                         itype='Wire', otype='Wire', with_enable=True)
# naive solution idea
# interface = RAMInterface(m, name + '_%d' % i, datawidth, addrwidth,
#                          itype='TmpWire', otype='TmpWire', with_enable=True)

However, the alternation ended up outputting verilog code like blow (comments are mine).

// expected verilog output
// wire [8-1:0] _tmp_50;
// actual verilog output
wire ["myram_addr"-1:0] _tmp_50 [0:8-1];

It seems that this happend since the keyword argument name of Wire was interpreted as width in TmpWire.

shtaxxx commented 1 year ago

This issue has been fixed in e7db2919d900debd23f548845b5f635b407ed231 .