When I try to switch automatically between TmpWire and Wire instead of using only Wire in codes like below (example from thread/ram.py), I thought it just works by replacing 'Wire' with 'TmpWire'.
interface = RAMInterface(m, name + '_%d' % i, datawidth, addrwidth,
itype='Wire', otype='Wire', with_enable=True)
# naive solution idea
# interface = RAMInterface(m, name + '_%d' % i, datawidth, addrwidth,
# itype='TmpWire', otype='TmpWire', with_enable=True)
However, the alternation ended up outputting verilog code like blow (comments are mine).
When I try to switch automatically between
TmpWire
andWire
instead of using onlyWire
in codes like below (example from thread/ram.py), I thought it just works by replacing'Wire'
with'TmpWire'
.However, the alternation ended up outputting verilog code like blow (comments are mine).
It seems that this happend since the keyword argument
name
ofWire
was interpreted aswidth
inTmpWire
.