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PyHDI / veriloggen

Veriloggen: A Mixed-Paradigm Hardware Construction Framework
Apache License 2.0
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Convention violation of AXI Lite protocol on AxiLiteSlave #50

Closed RyusukeYamano closed 1 year ago

RyusukeYamano commented 1 year ago

About

AxisLiteRegister now accepts outstandings of 2 in read transactions. The axi lite protocol requires that the number of outstandings be less than 1.

Expected

Set the maximum number of outstandings for AxiLiteSlave transactions to 1.

Environment

Debug

I suspect that the "ack" signal generated by push_read_data() in types/axi.py:AxiLiteSlave class is not correct. In thread/axis.py, this "ack" is observed and FSM of AXISLiteRegister is set back to init. The "ack" signal is not a handshake notification of rdata, but rather a push notification of rdata, so it make fsm into init, despite handshake for read channel has not been established. The fsm state returns to init even if the handshake has not been established, and the next address request is accepted. As a result, the number of outstandings seems to be more than 1.

shtaxxx commented 1 year ago

This issue has been resolved in c7dc37b95288a4a9e29b4e57a5e5fda11c0a16ca .