`types.AxiMaster` should be have a cap of number of outstanding readout transactions.

[RyusukeYamano]

About

We are currently using ARM's official AXI Protocol Checker which is AMBA 4 AXI4,AXI4-lite,AXI4-stream SVAs (BP063) to verify IP that is using veriloggen.AxiMaster.

veriloggen.types.AxiMaster can only specify the upper limit of the number of write transaction transfers by the outstanding_wcount_width of the write transaction, so the upper limit of the number of read transaction transfers is nondeterministic. This causes the simulator to fail in some cases.

   Axi4PC    // ARM Official Protocol Checker IP
      #(
         .DATA_WIDTH       ( AXI4_DW ),
         .WID_WIDTH        ( 0       ),
         .RID_WIDTH        ( 0       ),
         .AWUSER_WIDTH     ( 2       ),
         .WUSER_WIDTH      ( 0       ),
         .BUSER_WIDTH      ( 0       ),
         .ARUSER_WIDTH     ( 2       ),
         .RUSER_WIDTH      ( 0       ),
         .MAXRBURSTS       ( 1       ),    // <- We want to set this argument correctly.
         .MAXWBURSTS       ( 7       ),
         .MAXWAITS         ( 33      )
      )
      Axi4PC
      (
         // Global Signals
         .ACLK          ( clk           ),
         .ARESETn       ( rst_n         ),
         // Write Address Channel
         .AWID          ( maxi_awid     ),
         .AWADDR        ( maxi_awaddr   ),
         .AWLEN         ( maxi_awlen    ),
         .AWSIZE        ( maxi_awsize   ),
         .AWBURST       ( maxi_awburst  ),
         .AWLOCK        ( maxi_awlock   ),
         .AWCACHE       ( maxi_awcache  ),
         .AWPROT        ( maxi_awprot   ),
         .AWQOS         ( maxi_awqos    ),
         .AWREGION      ( maxi_awregion ),
         .AWUSER        ( maxi_awuser   ),
         .AWVALID       ( maxi_awvalid  ),
         .AWREADY       ( maxi_awready  ),
         // Write Channel
         .WLAST         ( maxi_wlast    ),
         .WDATA         ( maxi_wdata    ),
         .WSTRB         ( maxi_wstrb    ),
         .WUSER         ( maxi_wuser    ),
         .WVALID        ( maxi_wvalid   ),
         .WREADY        ( maxi_wready   ),
         // Write Response Channel
         .BID           ( maxi_bid      ),
         .BRESP         ( maxi_bresp    ),
         .BUSER         ( maxi_buser    ),
         .BVALID        ( maxi_bvalid   ),
         .BREADY        ( maxi_bready   ),
         // Read Address Channel
         .ARID          ( maxi_arid     ),
         .ARADDR        ( maxi_araddr   ),
         .ARLEN         ( maxi_arlen    ),
         .ARSIZE        ( maxi_arsize   ),
         .ARBURST       ( maxi_arburst  ),
         .ARLOCK        ( maxi_arlock   ),
         .ARCACHE       ( maxi_arcache  ),
         .ARPROT        ( maxi_arprot   ),
         .ARQOS         ( maxi_arqos    ),
         .ARREGION      ( maxi_arregion ),
         .ARUSER        ( maxi_aruser   ),
         .ARVALID       ( maxi_arvalid  ),
         .ARREADY       ( maxi_arready  ),
         // Read Channel
         .RID           ( maxi_rid      ),
         .RLAST         ( maxi_rlast    ),
         .RDATA         ( maxi_rdata    ),
         .RRESP         ( maxi_rresp    ),
         .RUSER         ( maxi_ruser    ),
         .RVALID        ( maxi_rvalid   ),
         .RREADY        ( maxi_rready   ),
         // Low power interface
         .CACTIVE       ( 1'b1          ),
         .CSYSREQ       ( 1'b1          ),
         .CSYSACK       ( 1'b1          )
   );

Expected

Set a cap on the number of outstanding read transactions for veriloggen.types.AxiMaster .

Environment

• Ubuntu 18.04.4 LTS
• Python 3.8.13
• pyverilog 1.3.0
• veriloggen v2.1.0 - v2.1.1

[RyusukeYamano]

I realized that we should have an axi-fixture module that can limit the number of read outstandings.