Multi instance using the same module

[panwenzong]

When doing multi instance with the same module, the module name is appended with "_" surfix. Code like:

m = Module("top") param = [] port = [] m.Instance("counter","i0",param,port) m.Instance("counter","i1",param,port) print(m.to_verilog())

The result likes:

module top ( );

counter i0 { };

counter_ i1 { };

endmodule

I can't figure out why there is a "_" at the end of reference name for the second instance declaration. Anyone has clue to this?

Thanks a lot!

[LucasBraganca]

This happens when you have two instances of objects with the same name, then Veriloggen treats them as two different modules as they have the same name. It adds an underscore to differentiate in Verilog.

m = Module("top")
param = []
port = []
counter = Module("counter")
m.Instance(counter,"i0",param,port)
m.Instance(counter,"i1",param,port)
print(m.to_verilog())

module top (

);

counter i0 ( );

counter i1 ( );

endmodule

module counter (

);

endmodule

[panwenzong]

This happens when you have two instances of objects with the same name, then Veriloggen treats them as two different modules as they have the same name. It adds an underscore to differentiate in Verilog.

m = Module("top")
param = []
port = []
counter = Module("counter")
m.Instance(counter,"i0",param,port)
m.Instance(counter,"i1",param,port)
print(m.to_verilog())

module top (

);

counter i0 ( );

counter i1 ( );

endmodule

module counter (

);

endmodule

It works!!! I temp to use str type Stubmodule and cause a "_". Thank you!!!

[panwenzong]

Multiple creation of module with the same module name causing a "_" appended at the end.

[shtaxxx]

I'm now considering to disable this behavior that appends _ to the module name.

[shtaxxx]

This issue has been resolved in 06b349032999548abd7520618cc41c773ad76c50 .