Abstract: This is a followup paper for "“A graph placement methodology for fast chip design“
Conclusion:
We extend the original work [1] in three perspectives. First,
we provide more details on the motivation and algorithm
design. Second, DREAMPlace is integrated into the original
framework. Finally, we conduct experiments on public benchmarks and make fair comparisons with academic tools
Yu: Not sure if it's the follow up from an earlier paper (see #49 ）though it's for floorplan and this is for placement?
In general it's an partial improvement paper based on 49.
Link: https://arxiv.org/pdf/2109.02587.pdf
Abstract: This is a followup paper for "“A graph placement methodology for fast chip design“
Conclusion: We extend the original work [1] in three perspectives. First, we provide more details on the motivation and algorithm design. Second, DREAMPlace is integrated into the original framework. Finally, we conduct experiments on public benchmarks and make fair comparisons with academic tools
Yu: Not sure if it's the follow up from an earlier paper (see #49 ）though it's for floorplan and this is for placement?
In general it's an partial improvement paper based on 49.