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QianfengClarkShen / Tbps_CRC

A SytemVerilog implementation of Cyclic Redundancy Check runs at up to Terabits per second
MIT License
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Slow simulation performance #4

Closed iwaniwaniwan012 closed 9 months ago

iwaniwaniwan012 commented 9 months ago

I have slow simulation performance, or if it expected? Simulation software - QuestaSim 10.7c Linux CRC Parameters - ByteEnabled version, bus width 512b, pipeline 1. CPU is rather good Intel i7-9700K, 64GB Ram

QianfengClarkShen commented 9 months ago

Could you be more specific? How slow was it? How many clock cycles can you simulate every minute? Have you try other simulators?

iwaniwaniwan012 commented 9 months ago

Could you be more specific? How slow was it? How many clock cycles can you simulate every minute? Have you try other simulators?

Thanks for advice, tested in ModelSim 10.2c and it work rather fast. In QuestaSim it simulates approx 100-150 clocks in minute

QianfengClarkShen commented 9 months ago

I would assume there is a workaround for you, therefore I will close the issue as not planned. I do not have a QuestaSim license and I am not planning to support it in the foreseeable future.