this adds circuit structure validation to staq. With this, staq fails most of the tests due to gates on edges that do not exist in the device topology. Not sure if this is an error on our part, or in their routines, but I have confirmed for some small instances that the gates at the output are indeed on edges that do not exist in the coupling map
this adds circuit structure validation to staq. With this, staq fails most of the tests due to gates on edges that do not exist in the device topology. Not sure if this is an error on our part, or in their routines, but I have confirmed for some small instances that the gates at the output are indeed on edges that do not exist in the coupling map