A circuit containing a SXGate with reverse_ops reports DAGCircuitError: 'bit mapping invalid: expected 1, got 2' after being qpy serialized and deserialized. Noticed that there's no error if not doing qpy serialization roundtrip.
How can we reproduce the issue?
from qiskit import QuantumCircuit,ClassicalRegister, QuantumRegister, transpile
from qiskit.circuit.library.standard_gates import SXGate
qr = QuantumRegister(2)
cr = ClassicalRegister(2)
qc = QuantumCircuit(qr, cr)
qc.append(SXGate().power(1).control(1).reverse_ops(), qr)
from qiskit import qpy
with open('circuit.qpy', 'wb') as fd:
qpy.dump(qc, fd)
with open('circuit.qpy', 'rb') as fd:
qc = qpy.load(fd)[0]
from qiskit_aer import Aer
backend = Aer.get_backend('qasm_simulator')
qc = transpile(qc, backend)
What should happen?
Traceback (most recent call last):
File "/mnt/tests/reproduction/reproduce_bit_mapping_invalid.py", line 17, in <module>
qc = transpile(qc, backend)
^^^^^^^^^^^^^^^^^^^^^^
File "/root/anaconda3/envs/qiskit46/lib/python3.11/site-packages/qiskit/compiler/transpiler.py", line 428, in transpile
out_circuits = pm.run(circuits, callback=callback)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/root/anaconda3/envs/qiskit46/lib/python3.11/site-packages/qiskit/transpiler/passmanager.py", line 561, in run
return super().run(circuits, output_name, callback)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/root/anaconda3/envs/qiskit46/lib/python3.11/site-packages/qiskit/transpiler/passmanager.py", line 580, in wrapper
return meth(*meth_args, **meth_kwargs)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/root/anaconda3/envs/qiskit46/lib/python3.11/site-packages/qiskit/transpiler/passmanager.py", line 308, in run
return super().run(
^^^^^^^^^^^^
File "/root/anaconda3/envs/qiskit46/lib/python3.11/site-packages/qiskit/passmanager/passmanager.py", line 224, in run
out_program = _run_workflow(
^^^^^^^^^^^^^^
File "/root/anaconda3/envs/qiskit46/lib/python3.11/site-packages/qiskit/passmanager/passmanager.py", line 286, in _run_workflow
passmanager_ir, final_state = flow_controller.execute(
^^^^^^^^^^^^^^^^^^^^^^^^
File "/root/anaconda3/envs/qiskit46/lib/python3.11/site-packages/qiskit/passmanager/base_tasks.py", line 218, in execute
passmanager_ir, state = next_task.execute(
^^^^^^^^^^^^^^^^^^
File "/root/anaconda3/envs/qiskit46/lib/python3.11/site-packages/qiskit/transpiler/basepasses.py", line 195, in execute
new_dag, state = super().execute(
^^^^^^^^^^^^^^^^
File "/root/anaconda3/envs/qiskit46/lib/python3.11/site-packages/qiskit/passmanager/base_tasks.py", line 98, in execute
ret = self.run(passmanager_ir)
^^^^^^^^^^^^^^^^^^^^^^^^
File "/root/anaconda3/envs/qiskit46/lib/python3.11/site-packages/qiskit/transpiler/passes/synthesis/high_level_synthesis.py", line 247, in run
decomposition, modified = self._recursively_handle_op(node.op, qubits)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/root/anaconda3/envs/qiskit46/lib/python3.11/site-packages/qiskit/transpiler/passes/synthesis/high_level_synthesis.py", line 336, in _recursively_handle_op
dag = self.run(dag)
^^^^^^^^^^^^^
File "/root/anaconda3/envs/qiskit46/lib/python3.11/site-packages/qiskit/transpiler/passes/synthesis/high_level_synthesis.py", line 247, in run
decomposition, modified = self._recursively_handle_op(node.op, qubits)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/root/anaconda3/envs/qiskit46/lib/python3.11/site-packages/qiskit/transpiler/passes/synthesis/high_level_synthesis.py", line 336, in _recursively_handle_op
dag = self.run(dag)
^^^^^^^^^^^^^
File "/root/anaconda3/envs/qiskit46/lib/python3.11/site-packages/qiskit/transpiler/passes/synthesis/high_level_synthesis.py", line 247, in run
decomposition, modified = self._recursively_handle_op(node.op, qubits)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/root/anaconda3/envs/qiskit46/lib/python3.11/site-packages/qiskit/transpiler/passes/synthesis/high_level_synthesis.py", line 336, in _recursively_handle_op
dag = self.run(dag)
^^^^^^^^^^^^^
File "/root/anaconda3/envs/qiskit46/lib/python3.11/site-packages/qiskit/transpiler/passes/synthesis/high_level_synthesis.py", line 247, in run
decomposition, modified = self._recursively_handle_op(node.op, qubits)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/root/anaconda3/envs/qiskit46/lib/python3.11/site-packages/qiskit/transpiler/passes/synthesis/high_level_synthesis.py", line 336, in _recursively_handle_op
dag = self.run(dag)
^^^^^^^^^^^^^
File "/root/anaconda3/envs/qiskit46/lib/python3.11/site-packages/qiskit/transpiler/passes/synthesis/high_level_synthesis.py", line 257, in run
dag.substitute_node_with_dag(node, decomposition)
File "/root/anaconda3/envs/qiskit46/lib/python3.11/site-packages/qiskit/dagcircuit/dagcircuit.py", line 1232, in substitute_node_with_dag
raise DAGCircuitError(
qiskit.dagcircuit.exceptions.DAGCircuitError: 'bit mapping invalid: expected 1, got 2'
Environment
What is happening?
A circuit containing a SXGate with reverse_ops reports DAGCircuitError: 'bit mapping invalid: expected 1, got 2' after being qpy serialized and deserialized. Noticed that there's no error if not doing qpy serialization roundtrip.
How can we reproduce the issue?
What should happen?
Any suggestions?
No response