(perhaps) x86: directly use kernel (interrupt) stack on interrupt instead of using GS

[shrik3]

Currently we have in interrupt::InitSingleton

pub unsafe fn InitSingleton() {
    let mut idt = idt::Idt::new();

    idt.set_handler(0, div_zero_handler).set_stack_index(0);

    idt.set_handler(1, debug_handler).set_stack_index(0);
    idt.set_handler(2, nm_handler).set_stack_index(0);
    idt.set_handler(3, breakpoint_handler)
        .set_stack_index(0)
        .set_privilege_level(3);
    idt.set_handler(4, overflow_handler).set_stack_index(0);
    idt.set_handler(5, bound_range_handler).set_stack_index(0);
    // ......
}

if I'm understanding correctly, it is using the user stack for interrupts by setting IDT.IST to 0.. And upon interrupts the code manually switch to kernel stack using the gs register.

    // switch to task kernel stack
    mov rdi, rsp
    // cs of call, if it from user, last 3 bit is 0b11
    mov rsi, [rsp + 11*8]
    //caused in user mode?
    and rsi, 0b11
    jz 1f
    //load kernel rsp
    swapgs
    mov rsp, gs:0
    jmp 2f
    1:
    //load exception rsp, which is kernel rsp
    mov rsi, [rsp + 13 *8]
    2:
    // ...

also for syscall:

syscall_entry:
    swapgs
    //user stack
    mov gs:8, rsp
    //kernel stack
    mov rsp, gs:0
    //reserve the space for exception stack frame
    sub rsp, 1 * 8
    // ....

It could be simpler to specify another stack in the IDT.IST and maintain the kernel stack address in the TSS instead of in the GS register.

IST: A 3-bit value which is an offset into the Interrupt Stack Table, which is stored in the Task State Segment.

This is not bug fix nor improvement. Just an idea of simplifying the low level code.

ref: https://wiki.osdev.org/Interrupt_Descriptor_Table

[shrik3]

well, it may not worth it and there is a potential performance issue with TSS.