Open shrik3 opened 5 months ago
CC. @QuarkContainer
The time stamp counter in newer processors may support an enhancement, referred to as invariant TSC. Processor’s support for invariant TSC is indicated by CPUID.80000007H:EDX[8]. The invariant TSC will run at a constant rate in all ACPI P-, C-. and T-states. This is the architectural behavior moving forward. On processors with invariant TSC support, the OS may use the TSC for wall clock timer services (instead of ACPI or HPET timers). TSC reads are much more efficient and do not incur the overhead associated with a ring transition or access to a platform resource.
In newer (x86) processors the TSC
increments at a constant rate, in which case perhaps there is not need to calibrate the system clock per CPU frequency if using the rdtsc
instruction.
reference: Intel SDM section 17.17.1 Invariant TSC
I don't know if it's only me but strace on quark (x86) repeatedly shows:
the vcpu constantly polls KVM_GET_TSC_KHZ, which always fails.
Perhaps we turn off this kvm capability, if we don't use it.