Wrong netlist for subcircuits with shorted ports

[in3otd]

This may be an old bug: I have checked that it's present also in Qucs 0.0.16 and could be the same issue mentioned in the BUGS file years ago.

When a subcircuit contains ports which are on the same net (shorted by a wire) the connections at top level are wrong. The simple circuit below has a subcircuit, SC1, which is just a short between the two ports and as you can see, the simulation result is wrong. Looking at the generated netlist

.Def:short_circuit _net0 _net0
.Def:End

Vdc:V1 in gnd U="1 V"
R:R1 out gnd R="50 Ohm" Temp="26.85" Tc1="0.0" Tc2="0.0" Tnom="26.85"
Sub:SC1 out in Type="short_circuit"
.DC:DC1 Temp="26.85" reltol="0.001" abstol="1 pA" vntol="1 uV" saveOPs="no" MaxIter="150" saveAll="no" convHelper="none" Solver="CroutLU"

it's clear that the two ports are actually not connected in the netlist.

If the subcircuit shorts the ports via a 0 ohm resistor the results are correct.

The above test project is in this netlist_bug.zip file.

[felix-salfelder]

what does "to withdraw the netlist" mean? did this involve a warning or error message back in 2007?

probably it's best to disallow more than one port per name -- cannot think of a use case...

[in3otd]

not sure what the simulator did in 2007, at that time Qucs was at version 0.0.13 and I do not have this version installed. May not be easy to compile from the sources now.

I saw this bug while trying to simulate a subcircuit with a resonant circuit to GND between the shorted ports - also in this case one of the subcircuit ports ends up unconnected.

[felix-salfelder]

where is the bug?

is it the missing warning/error? or is is the subcircuit definition? where does it come from?

.Def:short_circuit _net0 _net0
.Def:End

(it looks a bit strange, doesn't it?) FWIW, a verilog component that does what you apparently expect, could look like the following. note the lack of port name collision or magic involved.

module SC(a,b)
  [..]
  V(a,b)<+0.;
  [..]
endmodule

or spice

.subckt SC 1 2
Vshort 1 2 0
.ends

[in3otd]

if the "short circuit" subcircuit actually has an RLC parallel circuit to ground the netlist generated by Qucs is

.Def:short_circuit _net0 _net0
C:C1 gnd _net0 C="1 pF" V=""
R:R2 gnd _net0 R="50 Ohm" Temp="26.85" Tc1="0.0" Tc2="0.0" Tnom="26.85"
L:L1 gnd _net0 L="1 nH" I=""
.Def:End

Vdc:V1 in gnd U="1 V"
R:R1 out gnd R="50 Ohm" Temp="26.85" Tc1="0.0" Tc2="0.0" Tnom="26.85"
.DC:DC1 Temp="26.85" reltol="0.001" abstol="1 pA" vntol="1 uV" saveOPs="no" MaxIter="150" saveAll="no" convHelper="none" Solver="CroutLU"
Sub:SC1 out in Type="short_circuit"

then the flattened netlist built by qucsator is

  L:short_circuit.SC1.L1 gnd in L="1e-09H"
  R:short_circuit.SC1.R2 gnd in R="50Ohm" Temp="26.85" Tc1="0" Tc2="0" Tnom="26.85"
  C:short_circuit.SC1.C1 gnd in C="1e-12F"
  Vdc:V1 in gnd U="1V"
  R:R1 out gnd R="50Ohm" Temp="26.85" Tc1="0" Tc2="0" Tnom="26.85"
  DC:DC1 Temp="26.85" reltol="0.001" abstol="1e-12A" vntol="1e-06V" saveOPs="no" MaxIter="150" saveAll="no" convHelper="none" Solver="CroutLU"

so, where is the error? Can be in both: the qucs subcircuit definition may be correct, it has two ports which are actually on the same net. Then qucsator fails to keep the ports connected when flattening the netlist. Or we can say that the ports of a subcircuit must be on different nets, then qucs should generate a different netlist for this particular case.

[felix-salfelder]

Or we can say that the ports of a subcircuit must be on different nets

exactly. this follows directly from "a port defines a net". we should adhere to that. then, the bug is in the netlister: it confuses nets and ports.

eventually, we want a net to be a first level object (="component") which has ports (with coordinates). this will facilitate netlisting and schematic exchange quite a lot: netlisting becomes a no-op, because the schematic already is a netlist. and schematic exchage will be simple because we could use verilog (a standard, surprise!) for that.