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QuickLogic-Corp / quicklogic-fpga-toolchain

Open Source FPGA toolchain and documentation for QuickLogic devices and eFPGA IP
https://quicklogic-quicklogic-fpga-toolchain.readthedocs-hosted.com/en/latest/index.html
Apache License 2.0
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Large number of warnings from ql_symbiflow #39

Closed murthyvedula closed 3 years ago

murthyvedula commented 3 years ago

ql_symbiflow outputs large number of warnings of the type:

Warning 2443: Model 'RAM_CE1_FE1_D0_PR0_WSA0_WSB0_VPR' input port 'FIFO_EN_1' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)

This causes the CI builds to fail with the following error message:

The job exceeded the maximum log length, and has been terminated.

kkumar23 commented 3 years ago

@tpagarani : we had this issue . Any plans of fixing them ?

tpagarani commented 3 years ago

@kkumar23 I believe there is a flag to turn off these warnings. Can you confirm with @kgugala ?

kkumar23 commented 3 years ago

@kgugala Do we have any flag for these warnings ?

kkumar23 commented 3 years ago

@kgugala : Any flag you can suggest ?

kgugala commented 3 years ago

you need to add warn_model_missing_timing to a list provided with the suppress_warnings flag in VPR

kkumar23 commented 3 years ago

@murthyvedula : Please verify this fix in the symbiflow v1.3.0