/s3-gateware/projects/S3_AEC design doesn't work when open src tools are used

QuickLogic-Corp / s3-gateware

Gateware (HDL IPs) for EOS S3 MCU+eFPGA SoC

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/s3-gateware/projects/S3_AEC design doesn't work when open src tools are used #37

Open RandyO-QL opened 3 years ago

RandyO-QL commented 3 years ago

When compiled with Precision + SpDE, the bitfile works fine in hardware, but the bitfile created by ql-symbiflow doesn't. Siva can provide more details on the failure, but it appears that the I2S receiver occasionally adds an extra bit to the received data. I can't tell if this is a functional issue or timing.

anthonyle-ql commented 3 years ago

The issue with Symbiflow is the data collected via I2S may show wrong values.