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Bumps third_party/litex from
c401bdd
to804a1a5
.Commits
804a1a5
soc/add_uart: Improve error message for unsupported UART.73d70cf
build/sim/platform: Remove add_csr calls no longer required.525bbd1
Merge pull request #1465 from mohamedElbouazzati/cv32e41p_interrupts85e9881
Fix IRQS for cv32e41pda8d3d1
tools/litex_read_verilog: Add proc step before exporting to .json since now s...89670e5
soc/cores/spi: Add SPIBone import.519b411
core/spi/spi_bone: Update header.4e8e97a
cores/spi/spi_bone: Cosmetic cleanups on FSM (rename states).bdfb032
cores/spi/spi_bone: More cosmetic cleanups.0b05abb
cores/spi/spi_bone: Rename self.wishbone to self.bus/bus.Dependabot will resolve any conflicts with this PR as long as you don't alter it yourself. You can also trigger a rebase manually by commenting
@dependabot rebase
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