memory_libmap support for K6N10f

[rakeshm75]

1. SPRAM inferencing
2. DPRAM inferencing
3. Split support for SPRAM (placing 2 18K RAMs in a 36K block)
4. Asymmetric RAM support for SPRAM
5. Testcases to verify RAM inferencing, Split support & Asymmetric RAM inferencing

[rakeshm75]

@nakengelhardt No, there is no clock enable port separate from the write enable port. I will modify it.

[rakeshm75]

@nakengelhardt But I had kept the clken; on port W as well because the libmap_brams_map.v has PORT_W_CLK_EN & PORT_R_CLK_EN (even on the original TDP model, PORT_A_CLK_EN & PORT_B_CLK_EN ) & in the __QLF_SDP36K_MERGED module has PORT_A1_CLK_EN, PORT_B1_CLK_EN, PORT_A2_CLK_EN & PORT_B2_CLK_EN).

Actually on the BRAM primitive there is no write clock enable and no read clock enable. On read side there is Read enable signal (REN).

[nakengelhardt]

Yes, I needed to make it a clock enable for the R/W ports because you told me that if WEN is high the primitive will also update the read value, and the only way to represent that in the libmap logic is as clken. But if the ports aren't used simultaneously for read and write then there isn't any need to have a second signal because there is only one behavior (either the port is active or not). You can have rden; instead of clken; on the read port for the SDP, it shouldn't make a difference for a read-only port.

[nakengelhardt]

Would you want me to prepare to add support for the sdp-only architecture to the upstream synth_quicklogic, or is this still something you are only experimenting with?