Generated code for disassembler fails to handle instructions wider than 32bit (patch)

[Quuxplusone]

Bugzilla Link	PR13115
Status	RESOLVED FIXED
Importance	P normal
Reported by	Stefan Hepp (stefan@stefant.org)
Reported on	2012-06-15 05:24:53 -0700
Last modified on	2015-01-07 05:30:49 -0800
Version	trunk
Hardware	All All
CC	branko.drevensek@gmail.com, geek4civic@gmail.com, llvm-bugs@lists.llvm.org
Fixed by commit(s)
Attachments	0001-bugfix-for-handling-64bit-instructions-in-tablegen-p.patch (956 bytes, application/octet-stream) bugfix-for-handling-64bit-instructions-in-tablegen.patch (613 bytes, text/plain)
Blocks
Blocked by
See also

Created attachment 8718
Patch for handling wide instructions in tablegen disassembler emitter

TableGen emits the following code to extract fields from instructions in the
disassembler:

fieldMask = ((1 << numBits) - 1) << startBit;

If startbit is greater than 31 (e.g. for a 64bit wide instruction that has some
fields at bits above bit 31), the field mask always evaluates to zero, causing
problems for the disassembler.

I attached a small patch to fix this issue.

[Quuxplusone]

Cool. Please send patches to llvm-commits so it doesn't get lost.

[Quuxplusone]

Attached 0001-bugfix-for-handling-64bit-instructions-in-tablegen-p.patch (956 bytes, application/octet-stream): Patch for handling wide instructions in tablegen disassembler emitter

[Quuxplusone]

Attached bugfix-for-handling-64bit-instructions-in-tablegen.patch (613 bytes, text/plain): Fixed version of the bugfix patch

[Quuxplusone]

Fixed by this commit: https://github.com/llvm-mirror/llvm/commit/fc093def2d892a2ea068d3b9e6d5839c187cc942.