Open Quuxplusone opened 9 years ago
Bugzilla Link | PR24505 |
Status | NEW |
Importance | P normal |
Reported by | Chad Rosier (mcrosier@codeaurora.org) |
Reported on | 2015-08-19 13:37:38 -0700 |
Last modified on | 2015-09-11 10:26:14 -0700 |
Version | trunk |
Hardware | PC Windows NT |
CC | bmakam@codeaurora.org, bruno.cardoso@gmail.com, gberry@codeaurora.org, haicheng@codeaurora.org, junbuml@codeaurora.org, kristof.beyls@gmail.com, llvm-bugs@lists.llvm.org, mcrosier@codeaurora.org, mssimpso@codeaurora.org, quentin.colombet@gmail.com |
Fixed by commit(s) | |
Attachments | |
Blocks | |
Blocked by | |
See also |
Reintroduced in r245479.
Some useful notes:
1) This commit enables PHI lookup only for uncoalescable copy like instructions, such as cross reg class bitcasts. "one source + one destination bitcast" is one form of uncoalescable copies, but there are other forms that are currently handled, see PeepholeOptimizer::isUncoalescableCopy()
2) Although this commit introduced PHI lookup for uncoalescable copy like instructions, everything need to support PHI lookup for coalescable copies is there as well, I only didn't enabled it since I didn't get time to test it, this is also something worth investigating (maybe even more profitable than the uncoalescable case).
I am porting this optimization to AArch64 and find followings:
In x86, copies between different data types use different instructions such as MMX_MOVD64grr so that we can add flags for individual copy instructions like Bruno did.
In aarch64, the peephole optimization pass uses the standard pseudo COPY instruction to represent all data movement operations between scalar and vector registers. This COPY instruction is lowered to fmov in a later pass called “Post-RA pseudo instruction expansion pass” by calling AArch64InstrInfo::copyPhysReg.
Is there a good way to label the fmov instruction of aarch64 earlier so that the peephole optimization can recognize it?
(In reply to comment #2)
> I am porting this optimization to AArch64 and find followings:
>
> In x86, copies between different data types use different instructions such
> as MMX_MOVD64grr so that we can add flags for individual copy instructions
> like Bruno did.
>
> In aarch64, the peephole optimization pass uses the standard pseudo COPY
> instruction to represent all data movement operations between scalar and
> vector registers. This COPY instruction is lowered to fmov in a later pass
> called “Post-RA pseudo instruction expansion pass” by calling
> AArch64InstrInfo::copyPhysReg.
>
> Is there a good way to label the fmov instruction of aarch64 earlier so that
> the peephole optimization can recognize it?
You should add isbitcast in the td file.
Thank you, Quentin.
I tried to add isBitcast in td files before and it did not work.
The reason is that the real move instruction, fmov, is generated after the peephole optimization in AArch64. In the peeophole optimization, it is represented by the pseudo COPY instruction.