Open Quuxplusone opened 9 years ago
Bugzilla Link | PR24523 |
Status | NEW |
Importance | P normal |
Reported by | Sanjay Patel (spatel+llvm@rotateright.com) |
Reported on | 2015-08-20 12:27:45 -0700 |
Last modified on | 2020-03-27 08:07:00 -0700 |
Version | trunk |
Hardware | PC All |
CC | craig.topper@gmail.com, llvm-bugs@lists.llvm.org, llvm-dev@redking.me.uk |
Fixed by commit(s) | |
Attachments | |
Blocks | |
Blocked by | |
See also | PR24475 |
I looked at adding this to the SSE scalar intrinsics handling in
SimplifyDemandedVectorElts, for the ord/unord comparison cases we can add
support quite easily - the other cases would need more care due to SSE's quirky
NAN handling.
With a local patch, opt can generate this:
define float @my_sse_isnan(float %f1) {
%1 = fcmp uno float %f1, 0.0
%2 = sext i1 %1 to i32
%3 = bitcast i32 %2 to float
ret float %3
}
which results in the assembly:
xorl %eax, %eax
ucomiss %xmm0, %xmm0
movl $-1, %ecx
cmovnpl %eax, %ecx
movd %ecx, %xmm0
retq
Which is another can of worms....
Part of the problem is the fact that the original test reuses the same variable
in both arguments of the comparison, which stops SimplifyDemandedVectorElts
doing almost anything - we could fix this part of the bug very easily for cases
with different arguments.
I'm not sure which would be less work - adding basic support to
SimplifyDemandedVectorElts for values reused in an instruction or better
ucomiss/cmpss selection.
D17490 begins adding cmpss/cmpsd support to SimplifyDemandedVectorElts
4 years later...
Candidate patch: https://reviews.llvm.org/D76928