[aarch64] invalid operand for instruction on SIMD instructions

[Quuxplusone]

Bugzilla Link	PR25203
Status	NEW
Importance	P normal
Reported by	Riku Voipio (riku.voipio@linaro.org)
Reported on	2015-10-16 07:49:25 -0700
Last modified on	2016-01-14 06:02:55 -0800
Version	3.7
Hardware	PC Linux
CC	charlesturner7c5@gmail.com, james@jamesmolloy.co.uk, llvm-bugs@lists.llvm.org, rengolin@gmail.com
Fixed by commit(s)
Attachments
Blocks	PR18926
Blocked by
See also

-cut-
#include <stdio.h>

int main(void)
{
        asm("fmul v22.2s,v6.2s,v0.s[0]");
        asm("fmul v22.2s,v6.2s,v0.2s[0]");
        return 0;
}
-cut-

GCC is happy to assemble both forms of the instruction, but clang throws an
error on the second:

$ clang hello.c -o hello
<inline asm>:1:25: error: invalid operand for instruction
        fmul v22.2s,v6.2s,v0.2s[0]
                               ^
1 error generated.

It seems the parser is a bit too strict here.

[Quuxplusone]

This error was found while compiling chromium for arm64, which builds accelerated opemax code for aarch64 from:

https://chromium.googlesource.com/external/webrtc/deps/third_party/openmax/+/HEAD/dl/sp/src/arm/arm64/armSP_FFT_CToC_FC32_Radix4_s.S#185

[Quuxplusone]

Hi,

The ARMARM is clear on the syntax for this instruction. Why do you believe that the second form should be allowed?

Cheers,

James

[Quuxplusone]

(In reply to comment #2)
> The ARMARM is clear on the syntax for this instruction. Why do you believe
> that the second form should be allowed?

Compatibility with GCC? But indeed you are right, ARM ARM is quite explicit.
Feel free to close this bug.

[Quuxplusone]

On page C1-125 of the latest ARMARM, I see in section "SIMD vector element
names" the following,

"An assembler must accept a fully qualified SIMD register name, if the number
of lanes is greater than the index
value. See SIMD vector register names on page C1-124. For example, an assembler
must accept all of the following
forms as the name for the 32-bit element in bits [63:32] of the SIMD and
floating-point register V9:
V9.S[1]   //standard disassembly
V9.2S[1]  //optional number of lanes
V9.4S[1]  //optional number of lanes"

Which suggests to me this is legal use of the defined assembler syntax.