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[ARM] [backend] r289573 is causing favoring a long sequence of instructions. #30730

Open Quuxplusone opened 7 years ago

Quuxplusone commented 7 years ago
Bugzilla Link PR31757
Status NEW
Importance P normal
Reported by Sameer AbuAsal (sabuasal@codeaurora.org)
Reported on 2017-01-25 13:45:20 -0800
Last modified on 2017-01-26 15:59:04 -0800
Version trunk
Hardware PC Windows NT
CC alina.sbirlea@gmail.com, llvm-bugs@lists.llvm.org
Fixed by commit(s)
Attachments community_test.ll (3977 bytes, application/octet-stream)
Blocks
Blocked by
See also 
Created attachment 17895
Test case that include shuffle pattern.

Hi,

r289573 which changes the way strided store patterns are matched is causing the
Arm backend to generate longer sequesence of instruction for the attached IR.
Quuxplusone commented 7 years ago

Attached community_test.ll (3977 bytes, application/octet-stream): Test case that include shuffle pattern.

Quuxplusone commented 7 years ago 
Comment on attachment 17895
Test case that include shuffle pattern.

Couldn't attach the output assembly so I am listing them here:

good sequence (before patch):
@ BB#0:                                 @ %entry
        vld1.64 {d16, d17}, [r1]
        vld1.64 {d18, d19}, [r0]
        vorr    q10, q8, q8
        vuzp.8  q8, q10
        vzip.8  q9, q8
        vst1.64 {d18, d19}, [r2]
        vst1.64 {d16, d17}, [r2]
        bx      lr

Bad sequence (with patch):
@ BB#0:                                 @ %entry
        vld1.64 {d16, d17}, [r1]
        vld1.64 {d1, d2}, [r0]
        vorr    q9, q8, q8
        vuzp.8  q8, q9
        vorr    d18, d1, d1
        vorr    d3, d17, d17
        vorr    d19, d16, d16
        vst2.8  {d18, d19}, [r2:64]
        vst2.8  {d2, d3}, [r2:64]
        bx      lr

to recrete the problem:
llc test_case.ll -mtriple=armv7-linux-gnueabi -o out.s