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[X86] Account for domain crossing penalties in the scheduling of SSE/AVX instructions #31459

Open Quuxplusone opened 7 years ago

Quuxplusone commented 7 years ago
Bugzilla Link PR32487
Status NEW
Importance P enhancement
Reported by Simon Pilgrim (llvm-dev@redking.me.uk)
Reported on 2017-04-01 09:18:46 -0700
Last modified on 2018-06-01 02:49:46 -0700
Version trunk
Hardware PC All
CC andrea.dibiagio@gmail.com, clement.courbet@gmail.com, gchatelet@google.com, lebedev.ri@gmail.com, llvm-bugs@lists.llvm.org
Fixed by commit(s)
Attachments
Blocks PR32325
Blocked by
See also

X86 domain crossing penalties are a lot more complicated than we account for, each CPUs treat instructions from the same domain quite differently. We should be trying to better model this to allow instruction selection to better tune for particular CPUs.

Quuxplusone commented 6 years ago

This will probably need to be done through ReadAdvance entries somehow, it should be possible to do this for forwarding between resources as well (e.g. 1cy penalty for fp-add to vec-imul etc.).