[GlobalISel][AArch64] Calling convention for vectors incorrect on big-endian targets

[Quuxplusone]

Bugzilla Link	PR35360
Status	NEW
Importance	P enhancement
Reported by	Oliver Stannard (oliver.stannard@arm.com)
Reported on	2017-11-20 03:00:59 -0800
Last modified on	2017-12-04 07:39:57 -0800
Version	trunk
Hardware	PC Linux
CC	llvm-bugs@lists.llvm.org, quentin.colombet@gmail.com
Fixed by commit(s)
Attachments
Blocks
Blocked by	PR26161
See also

Global-isel generates incorrect code when targeting big-endian AArch64 for this
code:
  #include <arm_neon.h>
  int32x2_t load_vector(int32x2_t *p) {
    return *p;
  }

Global-isel generates this:
  // armclang --target=aarch64-arm-none-eabi -march=armv8-a -c callees.cpp -O0 -Wall -std=c++11 -mllvm -global-isel=true -mllvm -global-isel-abort=0 -mbig-endian -o - -S
  _Z11load_vectorP11__Int32x2_t:          // @_Z11load_vectorP11__Int32x2_t
  // BB#0:                                // %entry
          sub     sp, sp, #16             // =16
          str     x0, [sp, #8]
          ldr     x0, [sp, #8]
          ld1     { v0.2s }, [x0]
          add     sp, sp, #16             // =16
          ret

With global-isel off, there is a rev64 instruction between the ld1 and the add,
which fixes up the endianness of the vector.

[Quuxplusone]

Hi Amara, could you take a look?
Thanks.

[Quuxplusone]

This will require re-implementing the work James Molloy did a few years ago, it's documented here: https://llvm.org/docs/BigEndianNEON.html

For now since we are going to need to disable GISel for big endian due to the issue in https://bugs.llvm.org/show_bug.cgi?id=35359 this will also be disabled, thus it's no longer blocking enabling at -O0 for LE.