Open Quuxplusone opened 6 years ago
coalesce.mir
Created attachment 20864 reproducer Reproduce with llc -o - coalesce.mir -march=amdgcn -run-pass simple-register-coalescing -verify-machineinstrs which gives Use of $noreg does not have a corresponding definition on every path: 48r %2.sub0:sreg_64 = IMPLICIT_DEF LLVM ERROR: Use not jointly dominated by defs. -debug shows ... 0B bb.0: successors: %bb.1(0x80000000); %bb.1(100.00%) 16B %0:sreg_32 = IMPLICIT_DEF 32B %1:sreg_32 = IMPLICIT_DEF 48B undef %2.sub0:sreg_64 = IMPLICIT_DEF 64B %2.sub1:sreg_64 = COPY %1:sreg_32 ... ... 64B %2.sub1:sreg_64 = COPY %1:sreg_32 Considering merging to SReg_64 with %1 in %2:sub1 RHS = %1 [32r,64r:0) 0@32r weight:0.000000e+00 LHS = %2 [16r,48r:1)[48r,64r:2)[64r,80B:4)[80B,112B:6)[128r,144r:0)[144r,176B:3)[176B,240r:5) 0@128r 1@16r 2@48r 3@144r 4@64r 5@176B-phi 6@80B-phi L00000001 [48r,80B:1)[80B,112B:3)[128r,176B:0)[176B,224r:2) 0@128r 1@48r 2@176B-phi 3@80B-phi L00000002 [64r,80B:2)[80B,112B:4)[144r,176B:0)[176B,240r:3) 0@144r 1@x 2@64r 3@176B-phi 4@80B-phi weight:0.000000e+00 ... erased: 16r undef %2.sub1:sreg_64 = IMPLICIT_DEF erased: 64r %2.sub1:sreg_64 = COPY %1:sreg_32 erased: 32r %1:sreg_32 = IMPLICIT_DEF ... So we end up with this bb.0: 0B bb.0: successors: %bb.1(0x80000000); %bb.1(100.00%) 48B %2.sub0:sreg_64 = IMPLICIT_DEF Originally found when compiling for an out-of-tree target. Thanks to Matthias Braun for the above AMDGPU reproducer.
Attached coalesce.mir (502 bytes, text/plain): reproducer
coalesce.mir
(502 bytes, text/plain)