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[AMDGPU][MC] Many MIMG opcodes do not accept tfe with dmask:0xf #38273

Open Quuxplusone opened 5 years ago

Quuxplusone commented 5 years ago
Bugzilla Link PR39300
Status NEW
Importance P enhancement
Reported by Dmitry Preobrazhensky (d-pre@mail.ru)
Reported on 2018-10-15 09:18:32 -0700
Last modified on 2021-01-22 07:02:19 -0800
Version trunk
Hardware PC All
CC andrey.kasaurov@gmail.com, artem.tamazov@amd.com, i.am.perminov@gmail.com, jay.foad@gmail.com, llvm-bugs@lists.llvm.org, Matthew.Arsenault@amd.com, valery.pykhtin@gmail.com
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The reason for this issue is that current implementation does not support 5-register tuples.

Quuxplusone commented 3 years ago

I think this is fixed now. See https://reviews.llvm.org/D94960 which enabled proper disassembly of MIMG instructions with tfe.

Quuxplusone commented 3 years ago 
Thanks! The patch you mentioned did fix a lot of disassembler failures.

However some tests with 0xf dmask still fail to disassemble.

For example, the following code is disassembled ok for gfx8 and gfx9:

    0x00,0x0f,0x44,0xf0,0xfc,0x05,0x02,0x00
    image_atomic_cmpswap v[5:8], v252, s[8:15] dmask:0xf

The same code with tfe produces an invalid output for the same GPUs:

    0x00,0x0f,0x45,0xf0,0xfc,0x05,0x02,0x00
    image_atomic_cmpswap v[5:6], v252, s[8:15] dmask:0xf tfe

Also the following instruction fails to assemble on gfx7-gfx10:

    image_atomic_cmpswap v[5:9], v252, s[8:15] dmask:0xf tfe

See also related bugs 48846, 48847